1. Field of the Invention
The present invention relates to potential detect circuits, and more particularly, to a potential detect circuit for detecting whether the potential at the output node of a potential generation circuit has arrived at a predetermined target potential level or not.
2. Description of the Background Art
In a flash memory, data "0" or "1" is stored in a memory cell by drawing out or injecting charge from/to a floating gate of the memory cell (refer to FIG. 3). High voltage is required in drawing out or injecting the charge. The level of the high voltage must be set accurately in order to exactly control the amount of charge drawn out or injected with respect to the floating gate of the memory cell.
This high voltage is generated by a high voltage generation circuit (for example, a charge pump circuit) in the device. However, the voltage generated by the high voltage generation circuit is altered in accordance with the operating condition of the circuit (for example, the power supply voltage level and temperature). The operation of the high voltage generation circuit had to be controlled using a circuit that detects the high voltage.
FIG. 23 is a circuit diagram showing a structure of a conventional high voltage detect circuit. Referring to FIG. 23, this high voltage detect circuit includes two resistance elements 101 and 102 connected in series between an output terminal 100 of the high voltage generation circuit and the line of ground potential GND, a comparator 103 formed of P channel MOS transistors 104 and 105 and N channel MOS transistors 106 and 107, and an inverter 108. Resistance elements 101 and 102 form a voltage divider circuit. When the potential of output terminal 100 of the high voltage generation circuit is VP and the resistance values of resistance elements 101 and 102 are R5 and R6, respectively, the potential VO of a node N101 between resistance elements 101 and 102 is VO=VP.multidot.R6/(R5+R6).
MOS transistors 104 and 106 and MOS transistors 105 and 107 are connected in series between respective lines of power supply potential VCC and ground potential GND. P channel MOS transistors 104 and 105 have their gates both connected to the drain of P channel MOS transistor 104. P channel MOS transistors 104 and 105 form a current mirror circuit. N channel MOS transistors 106 and 107 receive potential VO and reference potential Vr5 at their gates, respectively. The drain of P channel MOS transistor 105 is the output node 103a of comparator 103. The output signal of comparator 103 is inverted by inverter 108 to become a high voltage detect signal /DE.
When potential VP is lower than the target potential and VO is lower than Vr5, the resistance value of N channel MOS transistor 106 becomes greater than the resistance value of N channel MOS transistor 107, whereby node 103a is pulled down to an L level to drive signal /DE to an H level. When potential VP exceeds the target potential and VO becomes higher than Vr5, the resistance value of N channel MOS transistor 106 becomes smaller than the resistance value of N channel MOS transistor 107, whereby node 103a is pulled up to an H level to drive signal /DE to an L level. The high voltage generation circuit is rendered active and inactive in response to signal /DE of an H level and an L level, respectively. Accordingly, the potential of output terminal 100 is maintained at the target potential.
FIG. 24 is a circuit block diagram showing a structure of another conventional high voltage detect circuit. The high voltage detect circuit of FIG. 24 differs from the high voltage detect circuit of FIG. 23 in that resistance element 101 is substituted with a variable resistance circuit 110.
Referring to FIG. 24, variable resistance circuit 110 includes a plurality (three in the drawing) of resistance elements 101a-10c connected in series between output terminal 100 and node N101, and P channel MOS transistors 111a-111c connected in parallel to resistance elements 101a-101c, respectively. P channel MOS transistors 111a-111c have their gates connected to a control circuit 112.
The conductive resistances of P channel MOS transistors 111a-111c are smaller than resistance values R5a-R5c of resistance elements 101a-101c. By rendering conductive a desired one of P channel MOS transistors 111a-111c by control circuit 112, resistance value R5 of variable resistance circuit 110 can be modified. Since VO/VP becomes smaller as resistance value R5 becomes greater, VP can be increased by matching VO with Vr5. In contrast, VO/VP becomes greater as resistance value R5 is reduced, so that VP can be set smaller by matching VO with Vr5. Therefore, by using this high voltage detect circuit and one charge pump, the level of the high voltage can be switched in response to change in resistance value R5 of variable resistance circuit 110.
In the above-described conventional high voltage detect circuit, the voltage conversion factor .DELTA.VO/.DELTA.VP becomes .DELTA.VO/.DELTA.VP=R6/(R5+R6). Since R6/(R5+R6)&lt;1, the voltage conversion factor becomes lower. A lower voltage conversion factor degrades the detection accuracy of the high voltage detect circuit, which in turn reduces the setting accuracy of the level of the high voltage.